Electronic packages used in high speed applications have an important function beyond the classical mechanical protection for the semiconductor devices that are packaged thereon. These types of packages should maintain semiconductor device performance during operation. When the switching speed of the devices goes above the 1 Gigahertz (GHz) clock rate, there is the need to consider the transmission of an electrical signal as the propagation of an electromagnetic wave, supported by current in a circuit trace, as a performance factor. This electromagnetic wave propagation is affected by the electronic packaging material properties such as dielectric constant as well as dielectric loss. There are other performance factors related to the electronic packaging structure (construction). One such performance factor has to do with the way electrical circuits are positioned in proximity to one another (tightly or widely spaced conductors). The sum of all these different factors affects the propagation of the electromagnetic waves in the electronic package. It is known that even if a material and a module structural configuration are defined there still may be unexpected low performance. It has been proven by simulation and measurements that propagation of an electromagnetic wave can also be severely affected by many kinds of discontinuities along its propagation path. These discontinuities can comprise changes in structure, material properties, and/or design features that the electrical signal encounters as it travels through the structure. These discontinuities can translate into electrical impedance (Z0) mismatches that are known to cause reflections of the signal.
All high speed electronic packages need to preserve the integrity of electromagnetic wave propagation, and this is achieved by designing and building circuit structures that have a well controlled transmission line impedance value. Controlling the impedance may not be sufficient due to the presence of other structures called parasitic elements (that may be capacitive, inductive and resistive) that become embedded within the package by the association of materials and electrical structures. These parasitic elements have very negligible effects in low speed digital applications but they can severely affect the signal propagation in high speed applications. As power levels decrease the effects of the parasitic elements become more pronounced (from the old TTL 5 V, down to 3.3 V, 2.5 V, 1.8 V, 1.2 V), leaving a very low margin to discriminate between the “up” level from the “zero” logical status.
A good way to visualize these effects is by analyzing the eye diagram of a measurement of a transmitted train of signals. By the size of the opening in the diagram it becomes easy to appreciate the quality of the transmitted information, as illustrated in FIGS. 1a and 1b. The more the “eye” closes, as illustrated on FIG. 1, the more difficult it is to determine whether switching transition has taken place or if the shift of the signal baseline is due to background noise.
It is possible to characterize all the “transitions”, also known as discontinuities, along the signal path and to understand and rank their negative contribution (detraction) to the overall package performance. In the ranking of negative effects the plated through hole (PTH) transition is one of the major detractors. The PTH transition effect has an inductive nature mated by a capacitive behavior when a portion of its structures is positioned close to other circuits. Such a combination acts, at high frequencies, as a low pass filter and therefore reduces the transmission line bandwidth.
In high speed applications, a design is accomplished in such a way that the transmission line has a known impedance (tailored to about 50 ohms). This is done by placing a reference ground plane under the layer that carries the transmission line circuit.
Impedance value is determined as follow:
                                          Z            0                    =                                    60                                                ɛ                                      r                    1                                                                        ⁢                          ln              ⁡                              (                                                      5.98                    ⁢                                                                                  ⁢                                          H                      2                                                                                                  0.8                      ⁢                      W                                        +                    T                                                  )                                                    ⁢                                  ⁢                  with          ,                                    (        1        )                                          ɛ                      r            1                          =                              ɛ            r                    ⁡                      [                          1              -                              exp                ⁡                                  (                                                                                    -                        1.55                                            ⁢                                                                                          ⁢                                              H                        1                                                                                    H                      2                                                        )                                                      ]                                              (        2        )            
wherein εr is the epoxy laminate dielectric constant, T is the copper thickness after plating, H1 is the dielectric thickness plus solder mask coating thickness, H2 is the dielectric thickness and W represents the line width as illustrated in FIG. 2.
These relationship's of the equations above can be applied to regular lines and surface circuit features. Unfortunately the traditional vertical transition (PTH) does not have the possibility to offer the same referenced structure with the current standard processes in place today.
To enhance the high speed performance in Surface Laminar Circuit (registered trademark of International Business Machines Corporation) products and Hyper BGA (registered trademark of International Business Machines Corporation) products, it is necessary to optimize the electric path for the electromagnetic wave. Design efforts have reduced and optimized circuit discontinuities affecting the propagating wave with low pass filtering effects reducing power and distorting shapes of the propagating waves. So far, the only exception, to the optimization work has been the vertical transition, PTH, or Resin Filled Plated Through Hole, RFP, used in the Surface Laminar Circuit technology.
FIG. 3a shows a partial perspective view of an electronic device carrier illustrating a standard PTH, wherein conductive layers 300 and 305 are separated by a core 310 of a electronic device carrier that may comprise conductive layers. Core 310 is made of dielectric material such as epoxy. Conductive layer 300 comprises a track 315 for transmitting a high speed signal that is shielded by conductive track 320. Likewise, conductive layer 305 comprises track 325 that is shielded by conductive track 330. Conductive tracks 315 and 325 are electrically connected to PTH 335. PTH 335 can be formed by drilling core 310 and filling the drilled hole with conductive material or plating the drilled hole vertical wall.
FIG. 3b depicts a partial cross section view of an electronic device carrier illustrating a known PTH and RFP. For sake of illustration, a core 350 of an electronic device carrier comprises two internal conductive layers and a conductive layer on each side, i.e. core 350 has 2 signal layers and 2 power planes also known in the industry as a 2S2P core. Each side of the core is covered with a dielectric material 355, e.g. epoxy, on which external conductive tracks may be designed, e.g. conductive track 360. Electrical connections between tracks on core 350 can be accomplished by either a PTH or RFP. In this example, RFP 365 connects several conductive tracks of core 350. An RFP is formed by drilling core 350, plating the hole wall with conductive material to form a cylinder and filling the cylinder with dielectric material such as epoxy, as illustrated. Likewise, PTH 370 connects several conductive tracks of core 350.
These vertical transitions can affect 100% of high speed signals that need to go through the central core of laminate electronic device carriers. Therefore these transitions have the highest impact on signal transmission.
Accordingly there is a need in the art for an improved multiple layer high density electronic device carrier that overcomes the shortcomings of the prior art as described above.